1. Field of the Invention
The present invention relates generally to a dynamic type semiconductor memory device, more particularly to such device comprising three-transistor type memory cells.
2. Description of the Prior Art
FIG. 1A is a schematic block diagram of a serial access memory.
Referring to FIG. 1A, a memory cell array 61 comprises a plurality of three-transistor type memory cells arranged in l rows and m columns. A memory cell to which data is to be written is selected by a write row selecting ring pointer 62 and a write column selecting ring pointer 64. In addition, a memory cell from which data is to be read out is selected by a read row selecting ring pointer 63 and a read column selecting ring pointer 65. The write column selecting ring pointer 64 comprises a write control circuit, and the read column selecting ring pointer 65 comprises a read control circuit.
A serial access memory generally is one in which the order of accessing memory cells in a memory cell array is determined. In this serial access memory, access is made in the order as shown in FIG. 1B. More specifically, access to memory cells is made in the order from a memory cell in the first row in the first column to a memory cell in the l-th row in the first column. Then, access to memory cells is made in the order from a memory cell in the first row in the second column to a memory cell in the l-th row in the second column. In the above described manner, when access to a memory cell in the l-th row in the m-th column is completed, access is made in the order, beginning with a memory cell in the first row in the first column in the same manner.
In FIG. 1A, first, the write row selecting ring pointer 62, the write column selecting ring pointer 64, the read row selecting ring pointer 63 and the read column selecting ring pointer 65 are initialized in response to a write reset WRST and a read reset signal RRST which are externally applied, respectively. As a result, the first row in the first column of the memory cell array 61 is designated. Thereafter, the second row, the third row, . . . , the l-th row in the first column are sequentially designated and then, the first row, the second row, . . . , the l-th row in the second column are sequentially designated in synchronization with a write clock WCLK and a read clock RCLK whlch are externally applied, respectively. After the l-th row in the m-th column is designated, the first row in the first column is designated. Thereafter, the same addressing is repeated until the write reset signal WRST and the read reset signal RRST are inputted. Input data DI is written by the write control circuit to a memory cell designated by the write row selecting ring pointer 62 and the write column selecting ring pointer 64. Information stored in a memory cell designated by the read row selecting ring pointer 63 and the read column selecting ring pointer 65 is read out as output data DO from the read control circuit. Write operation and read operation are performed independently each other.
FIG. 2 is a circuit diagram showing structure of main portions of the serial access memory shown in FIG. 1A.
A write bit line WB.sub.k and a read bit line RB.sub.k are provided corresponding to each column of the memory cell array 61, where k is any of integers from 1 through m. A write driver 11 is connected to each write bit line WB.sub.k and a read circuit 13 is connected to each read bit line RB.sub.k. In addition, a write word line WWL.sub.n and a read word line RWL.sub.n are provided corresponding to each row of the memory cell array 61, where n is any of integers from 1 through l. A write selecting gate 12 comprising an AND gate is provided corresponding to each of memory cells 10. FIG. 2 illustrates memory cells 10 in the n-th row, the (n +1)-th row and the (n+2)-th row in the k-th column and the (k+1)-th column of the memory cell array 61. Each of the memory cells 10 is a three-transistor type memory cell comprising transistors 1, 2 and 3. Each of the transistors 1, 2 and 3 comprises an N channel MOS field effect transistor. Numeral 4 denotes a storage capacitance.
Let's consider the memory cell 10 in the n-th row in the k-th column. The transistor 3 has its gate connected to the write bit line WB.sub.k through the transistor 1, its drain connected to the read bit line RB.sub.k through the transistor 2 and its source connected to ground. The transistor 1 has its gate connected to an output of the write selecting gate 12. The transistor 2 has its gate connected to the read word line RWL.sub.n. The write selecting gate 12 has one input terminal connected to the write word line WWL.sub.n. The write word line WWL.sub.n is connected to the write row selecting ring pointer 62 shown in FIG. 1. The read word line RWL.sub.n is connected to the read row selecting ring pointer 63.
The write selecting gates 12 in each column have respective other input terminals all receiving a write column selecting signal WBS.sub.k by the write column ring pointer 64. In addition, the read circuit 13 in each column receives a read column selecting signal RBS.sub.k by the read column selecting ring pointer 65.
Description is now made on the write operation of the serial access memory.
For example, when the memory cell 10 in the n-th row in the (k+1)-th column is selected by the write row selecting ring pointer 62 and the write column selecting ring pointer 64 shown in FIG. 1A, a potential on the write word line WWL.sub.n rises to an "H" level and a write column selecting signal WBS.sub.k+1 rises to the "H" level. Thus, an output of the write selecting gate 12 in the n-th row in the (k+1)-th column attains the "H" level, so that the transistor 1 is turned on. As a result, input data DI buffered by the write driver 11 is written to the storage capacitance 4 in the memory cell 10 through the write bit line WB.sub.k+1.
At that time, since write column selecting signals WBS in columns other than the (k+1)-th column and potentials on write word lines WWL in rows other than the n-th row are at an "L" level, outputs of write selecting gates 12 other than the write selecting gate 12 in the n-th row in the (k+1)-th column are at the "L" level. Thus, all of transistors 1 in memory cells 10 in columns other than the (k+1)-th column and rows other than the n-th row are turned off, so that information stored in the memory cells 10 are not destroyed.
Description is now made on the read operation of the serial access memory.
For example, when the memory cell 10 in the n-th row in the (k+1)-th column is selected by the read row selecting ring pointer 63 and the read column selecting ring pointer 65, a potential on the read word line RWL.sub.n rises to the "H" level. At that time, all of information stored in memory cells 10 in the n-th row are read out to read bit lines RB.sub.1 to RB.sub.m. However, the information are outputted only from the read circuit 13 in the (k+1)-th column selected by the read column selecting signal RBS.sub.k+1.
An FIFO (first in first out) memory which is one kind of serial access memory comprising three-transistor type memory cells is described in "Introduction to NMOS and CMOS VLSI System Design", pp. 268 to 273.
In the above described conventional semiconductor memory device comprising three-transistor type memory cells, since a gate circuit for selecting a memory cell to which information is to be written is required, the scale of a circuit becomes large by the gate circuit and the area to be occupied is increased. For example, if a single CMOS gate circuit is provided for every 8-bit memory cells (eight memory cells), the area occupied by the gate circuit becomes approximately 35% of the area of the entire memory cell array. In addition, if the gate circuit comprises a CMOS, a latch-up may be caused. The latch-up is a phenomenon that a circuit failure occurs by thermal radiation.